1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a memory cell, including a floating body transistor, and a method of operating the same.
2. Description of the Related Art
A typical dynamic memory cell in a semiconductor memory device includes an access transistor and a corresponding data storage capacitor. Data “1” is stored when there is a charge in the capacitor, and data “0” is stored when there is no charge in the capacitor. However, the capacitor charge dissipates after a predetermined time lapses, and thus the capacitor needs to be periodically refreshed (re-stored). A semiconductor memory device, which has a memory cell array including dynamic memory cells having such capacitors, is limited with respect to reducing the semiconductor memory device layout size.
Therefore, transistors having floating bodies were developed. A floating body transistor stores a majority carrier, and needs to be refreshed since the stored majority carrier dissipates after a predetermined time lapses. A memory cell including a floating body transistor does not have a capacitor, but it is used as a dynamic memory cell because it operates similarly to the capacitor with respect to being refreshed. Since one transistor having a floating body constitutes one memory cell, the layout size of the semiconductor memory device fabricated with floating body transistors may be significantly smaller than a semiconductor memory device fabricated with the typical capacitor memory cells, assuming the two types of semiconductor memory devices have the same capacity.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor memory device having a memory cell with a floating body transistor. The semiconductor memory device of FIG. 1 includes memory cell array blocks BLK1 and BLK2, bit line selectors 10-11 to 10-1m and 10-21 to 10-2m, a reference bit line selector 12-1, level limiters 14-1 to 14-m and 14-(m+1), sense amplifiers 16-1 to 16-m, a reference voltage generator 18, comparators COM1 to COMm, latches LA1 to LAm, write back gates WBG1 to WBGm, read column selecting gates RG1 to RGm, write column selecting gates WG1 to WGm, and a reference write column selecting gate RWG.
The functions of the components of FIG. 1 are described below. During a write operation, in the memory cells MC and the reference memory cells RMC of each of the memory cell array blocks BLK1 and BLK2, when a voltage of a predetermined level (e.g., 1.5V) is applied to a corresponding word line and a voltage having a level higher than a predetermined level (e.g., 1.5V) is applied to a corresponding bit line, electron-hole pairs are produced around a drain of the NMOS transistors, which form the memory cells due to impact ionization. The electrons among the electron-hole pairs are absorbed into the drain of the NMOS transistor and holes among the electron-hole pairs are stored in the floating body, thereby writing data “1”. That is, when data “1” is written, the NMOS transistor operates in a floating region. In contrast, when a voltage of a predetermined level (e.g., 1.5V) is applied to a corresponding word line and a voltage having a level lower than a predetermined level (e.g., −1.5V) is applied to a corresponding bit line, the floating body and the drain of the NMOS transistor are biased in a forward direction, so that most of the holes stored in the floating body are discharged to the drain, thereby writing data “0”. When data “1” is stored, a threshold voltage of the NMOS transistor is reduced, and when data “0”, is stored, a threshold voltage of the NMOS transistor is increased.
During a read operation, when a voltage of a predetermined level (e.g., 1.5V) is applied to a corresponding word line and a voltage (e.g., 0.2V) for making the transistor operate in a linear region is applied to a corresponding bit line, a current difference occurs in the corresponding bit line, and data “0” and data “1” are read by sensing the current difference. When the memory cell stores data “1”, since the threshold voltage is low, the bit line current of when data “1” is read becomes greater.
When the memory cell stores data “0”, since the threshold voltage is high, the bit line current of when data “0” is read becomes smaller. The bit line selectors 10-11 to 10-1m and 10-21 to 10-2m respectively select one of k bit lines BL1 to BLk of each of sub memory cell array blocks SBLK11 to SBLK1m and SBLK21 to SBLK2m to be connected to corresponding sense bit lines SBL1 to SBLm in response to bit line selecting signals BS1 to BSk. Each of the reference bit line selectors 12-1 and 12-2 connects reference bit lines RBL1 and RBL2 of each of the reference memory cell array blocks RBLK1 and RBLK2 to a reference bit line RSBL in response to corresponding reference bit line selecting signals RBS1, 2. The level limiters 14-1 to 14-m and 14-(m+1) respectively block corresponding current Ic1 to Ic(m+1) from being supplied to the corresponding sense bit lines SBL1 to SBLm and the reference sense bit line RSBL when the sense bit lines SBL1 to SBLm and the reference sense bit line RSBL are higher in voltage level than a restriction voltage level VBLR. That is, when the restriction voltage level is set to about 0.2V, a voltage for a read operation is applied to the bit lines BL1 to BLk and the reference bit lines RBL1 and RBL2 by the level limiters 14-1 to 14-(m+1), so that the corresponding currents Ic to Ic(m+1) flow.
The restriction voltage is set to 0.2V, which is relatively low, because when the restriction voltage is set to a voltage greater than 0.2V, the NMOS transistor having a floating body is biased in a saturation state, so that data “0” may be read as “1” due to the impact ionization. The reference voltage generator 18 generates a reference voltage VREF depending on the current Ic(m+1). The sense amplifiers 16-1 to 16-m detect the corresponding current Ic1 to Icm to generate voltages depending on the corresponding current Ic1 to Icm, respectively. The reference voltage VREF output from the reference voltage generator 18 has a voltage value between a voltage corresponding to data “0” and a voltage corresponding to data “1,” which are respectively output from the sense amplifiers 16-1 to 16-m.
A conventional semiconductor memory device like that of FIG. 1 is disclosed, for example, in U.S. Patent Application Publication No. 2003-231524, and semiconductor memory devices which include floating body memory cells and reference memory cells are disclosed, for example, in U.S. Patent Application Publication No. 2005-68807, and U.S. Pat. Nos. 6,567,330 and 6,882,008.
However, conventional semiconductor memory devices having floating body memory cells have complicated circuit configurations, which include, for example, reference memory cells, level limiters, sense amplifiers (current sense amplifiers), comparators, latches, and write back gates, in order to perform a read operation, as shown in FIG. 1. Also, the operation and control of such semiconductor memory devices are complicated. In addition, the conventional semiconductor memory devices having floating body memory cells should perform a refresh operation (re-storing operation) after the read operation.